Texas Instruments SCANSTA111MT/NOPB, 7-Bit Addressable Scan Port, 3 → 3.6 V, 48-Pin TSSOP

Technical data sheets
Legislation and Compliance
RoHS Certificate of Compliance
Product Details

Addressable JTAG Port, Texas Instruments

The Texas Instruments SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multi-drop test bus environment with the advantages of improved test throughput, and the ability to remove a board from the system whilst retaining test access to the remaining system modules. Each device supports up to three local IEEE 1149.1 scan rings which can be serially combined or accessed individually. A 32-bit TCK counter enables built-in self-test operations to be performed on one port while other scan chains are simultaneously tested.

The IEEE 1149.1 standard test access port and boundary-scan architecture uses devices known by the JTAG acronym, from Joint Test Action Group, and is used for testing and debugging system ports and PCB assemblies. Most embedded systems employ JTAG ports to enable in-circuit debugging and firmware programming, in addition to boundary scan testing.

Attribute Value
Number of Element Inputs 7
Number of Elements per Chip 1
Mounting Type Surface Mount
Package Type TSSOP
Pin Count 48
Dimensions 12.6 x 6.2 x 1.05mm
Length 12.6mm
Width 6.2mm
Height 1.05mm
Maximum Operating Supply Voltage 3.6 V
Maximum Operating Temperature +85 °C
Minimum Operating Supply Voltage 3 V
Minimum Operating Temperature -40 °C
Operating Temperature Range -40 → +85 °C
Operating Supply Voltage Range 3 → 3.6 V
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