- RS Stock No.:
- 216-6209
- Mfr. Part No.:
- 85104AGILF
- Manufacturer:
- Renesas Electronics
This product is currently unavailable to backorder.
Unfortunately, we don’t have this product in stock and it’s not available to backorder at this time.
Price Each (In a Tube of 74)
€15.041
(exc. VAT)
€18.50
(inc. VAT)
Units | Per unit | Per Tube* |
---|---|---|
74 + | €15.041 | €1,113.034 |
*price indicative
- RS Stock No.:
- 216-6209
- Mfr. Part No.:
- 85104AGILF
- Manufacturer:
- Renesas Electronics
Technical data sheets
Legislation and Compliance
Product Details
The Renesas Electronics 85104I is a low skew, high performance 1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
Four 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Additive phase jitter, RMS: 0.22ps (typical)
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximum)
Additive phase jitter, RMS: 0.22ps (typical)
Specifications
Attribute | Value |
---|---|
Logic Function | Clock Buffer |
Number of Clock Inputs | 5 |
Package Type | TSSOP |
Pin Count | 20 |