Zerynth MOD-M1-01-F016 3.6V WiFi Module, 802.11b/g/n
- RS Stock No.:
- 220-8451
- Mfr. Part No.:
- MOD-M1-01-F016
- Manufacturer:
- Zerynth
Subtotal (1 unit)*
€9.01
(exc. VAT)
€11.08
(inc. VAT)
Last RS stock
- Final 22 unit(s), ready to ship from another location
Units | Per unit |
|---|---|
| 1 + | €9.01 |
*price indicative
- RS Stock No.:
- 220-8451
- Mfr. Part No.:
- MOD-M1-01-F016
- Manufacturer:
- Zerynth
Specifications
Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Zerynth | |
| Supported Protocol | 802.11b/g/n | |
| Supply Voltage | 3.6V | |
| Dimensions | 22.5 x 18 x 3.1mm | |
| Select all | ||
|---|---|---|
Brand Zerynth | ||
Supported Protocol 802.11b/g/n | ||
Supply Voltage 3.6V | ||
Dimensions 22.5 x 18 x 3.1mm | ||
- COO (Country of Origin):
- IT
The TOI - Things On Internet ZM1 Module mounts on-board the ESP32-D0WD microcontroller, and is designed to be scalable and adaptive. The CPU clock frequency is adjustable from 80 MHz to 240MHz. The chip also has an embedded 16 MB of SPI Flash memory and integrates a rich set of peripherals, ranging from Hall sensors, Capacitive touch sensor, SD interface, Ethernet, High speed SPI, UART, I2S e I2C. Inside the ZM1, the crypto element ATECC608A from Microchip has been integrated to handle secure connections in an easy manner, exchanging certificates and keys, encrypting messages over TLS protocol and using secure authentication procedures.
448 KB of ROM for booting and core functions
520 KB of on-chip SRAM for data and instructions
8 KB of SRAM in RTC used for data storage it is accessed by the main CPU during RTC Boot from the Deep-sleep mode
8 KB of SRAM in RTC accessed by the co-processor during the Deep-sleep mode
1 Kbit of eFuse: 256 bits are used for the system (MAC address and chip configuration) and the remaining
768 bits are reserved for customer applications, including flash-encryption and chip-ID
520 KB of on-chip SRAM for data and instructions
8 KB of SRAM in RTC used for data storage it is accessed by the main CPU during RTC Boot from the Deep-sleep mode
8 KB of SRAM in RTC accessed by the co-processor during the Deep-sleep mode
1 Kbit of eFuse: 256 bits are used for the system (MAC address and chip configuration) and the remaining
768 bits are reserved for customer applications, including flash-encryption and chip-ID
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